- BSP SMP Interface definition with implementations for
- Simple SMP Aware Priority Based Scheduler
- Faithful SMP safe version of RTEMS OS Critical Sections
- Dispatch Disable
- Interrupt Disable
- Scheduler Simulator
- Test scenarios for new Simple SMP Scheduler
- Features Not Present
- Processor affinity
- Deferred Floating Point context switch
- Taking a core offline
Gedare Bloom and I made the first steps last summer when implemented the Pluggable Scheduler Framework for RTEMS and I added a "per cpu" data structure. Together these allow us to provide an alternative scheduler that is SMP aware and to have the data required by RTEMS SuperCore to manage each core encapsulated and allocated properly.
Jennifer Averett and I have been working the past couple of months on completing the SMP support to RTEMS. Jennifer and I are approaching a milestone of having a basic SMP system functional with the only major missing item being SMP safe interrupt disable sections. We are about to file a set of PRs and merge our current work and it made sense to post a blog entry with status that the PRs could reference.
- Test code - our test code is hacky since it has to force interprocessor interrupts. We need to integrate where these are generated inside RTEMS. Tests will be submitted once the code is in shape to work without "user-level" intervention.
- Simple SMP Scheduler - implemented, tested with schedsim and our hacky test
- Scheduler Simulator - multiple changes to improve its use during Scheduler development and to track changes in code base
- PC386 BSP - SMP BSP support seems complete.
- LEON3 BSP - SMP BSP support seems complete.
- Context Switch Disable Critical Section - Working
The next major tasks are to integrate the generation of interprocessor interrupts for subsequent dispatch requests and system shutdown. We also have to address interrupt disable SMP safety.
We are doing our best to break this into as many small incremental pieces as possible so the review and integration into the main tree is easier.